[i8x] Cpu Update #7: An Architectural Change.
QSmally QSmally
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 Published On Nov 2, 2018

Another step closer to the final release!

[CpuUpdate] - And after a long time of planning, designing, building, rebuilding, and testing, this is what I have, YET. There are more updates to come, so stay tuned for it!

I haven’t been active, much. Mainly because I’m busy with other stuff.

Here’s the IS Sheet.
https://docs.google.com/spreadsheets/...

This CPUs Features in This Video:
Complete rebuild of the CPU.
A lot of information.
New plans, new IS.

All Features:
Dataloop,
Serialised Program Memory (Can get programs throughout the program),
Storage (8 Pages * 32 Bytes),
Memory (32 Bytes).
Scheduled and unscheduled Interrupts,
CPU Network.

Overall Information:
7 Bytes Of Registers,
32 Bytes Of Memory,
Compacted And Optimised ALU,
PMem (Serial Based Input System),
Interrupt Handler (8 Interrupts),
8 External IO Ports (3Bit Address Bus).

Credit to:
Koyarno, for the magical registers.

Join the ORE Server! - MC.OPENREDSTONE.ORG
To get to the CPU warp, use /warp #i8x!
Thanks to Kevin Graham for the music!
“Apex” -    • Video  

Thank you all for watching this video, and I’ll see ya next time!

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