Welcome to the 2nd of our "FPGA from Zero to Hero - Live (4K) and Free Lectures". I am an FPGA engineer with 15 years of experience, and here is my LinkedIn profile   / koray-karakurt  . You may subscribe and join our YouTube channel in order to support and encourage us 😊 Thanks in advance 🙏

Our English Discord Server:   / discord  
Our Turkish Discord Server:   / discord  

Our Curriculum (15 weeks, 30 lectures) is as follows:

WEEK 01
Course-01 (29-SEP-24, at 10 A.M. GMT+2)
8 Major Steps of FPGA Design and Verification
https://youtube.com/live/j1uc9wGHP1s
Course-02 (29-SEP-24, at 01 P.M. GMT+2)
Q&A
https://youtube.com/live/77AiCSjF1W0

WEEK 02
Course-03 (02-OCT-24, at 08 P.M. GMT+2)
VHDL versus Verilog versus SystemVerilog
https://youtube.com/live/kBtmiuDApQQ
Course-04 (06-OCT-24, at 10 A.M. GMT+2)
Q&A
https://youtube.com/live/fWZainGbmSk

WEEK 03
Course-05 (TBD)
Linting Rules for FPGA Design and Verification
Course-06 (TBD)
Q&A

WEEK 04
Course-07 (TBD)
Git, Bitbucket, Jira and CI/CD Pipelines
Course-08 (TBD)
Q&A

WEEK 05
Course-09 (TBD)
Good Coding Practices and Design Recommendations - 1/3
Course-10 (TBD)
Q&A

WEEK 06
Course-11 (TBD)
Good Coding Practices and Design Recommendations - 2/3
Course-12 (TBD)
Q&A

WEEK 07
Course-13 (TBD)
Good Coding Practices and Design Recommendations - 3/3
Course-14 (TBD)
Q&A

WEEK 08
Course-15 (TBD)
Constraining Designs and Analyzing Timing Results - 1/2
Course-16 (TBD)
Q&A

WEEK 09
Course-17 (TBD)
Constraining Designs and Analyzing Timing Results - 2/2
Course-18 (TBD)
Q&A

WEEK 10
Course-19 (TBD)
Clock Domain Crossing (CDC) Issues and Solutions
Course-20 (TBD)
Q&A

WEEK 11
Course-21 (TBD)
Signal Tap Logic Analyzer and Integrated Logic Analyzer (ILA)
Course-22 (TBD)
Q&A

WEEK 12
Course-23 (TBD)
Self-Checking Testbenches and HDL Assertions
Course-24 (TBD)
Q&A

WEEK 13
Course-25 (TBD)
Code Coverage (CC) and Functional Coverage (FC)
Course-26 (TBD)
Q&A

WEEK 14
Course-27 (TBD)
Regression, Qualification and System Integration with CI/CD
Course-28 (TBD)
Q&A

WEEK 15
Course-29 (TBD)
10 Mbps to 800 Gbps Ethernet Applications on FPGAs
Course-30 (TBD)
Final Q&A